The present technology relates to operation of memory devices.
A charge-trapping material can be used in memory devices to store a charge which represents a data state. The charge-trapping material can be arranged vertically in a three-dimensional (3D) stacked memory structure, or horizontally in a two-dimensional (2D) memory structure. One example of a 3D memory structure is the Bit Cost Scalable (BiCS) architecture which comprises a stack of alternating conductive and dielectric layers. A memory hole is formed in the stack and a NAND string is then formed by filling the memory hole with materials including a charge-trapping layer. A straight NAND string extends in one memory hole, while a pipe- or U-shaped NAND string (P-BiCS) includes a pair of vertical columns of memory cells which extend in two memory holes and which are joined by a bottom back gate. Control gates of the memory cells are provided by the conductive layers.
The memory cells can be used to store two ranges of charges and, therefore, the memory cell can be programmed/erased between two data states (an erased state and a programmed state). Such a flash memory device is sometimes referred to as a binary memory device.
A multi-state memory device stores multiple bits of data per memory cell by identifying multiple distinct valid threshold voltage distributions (or data states) separated by forbidden ranges. Each distinct threshold voltage distribution corresponds to a predetermined value for the set of data bits encoded in the memory device. For example, a memory cell that stores two bits of data uses four valid threshold voltage distributions. A memory cell that stores four bits of data uses sixteen valid threshold voltage distributions.
As the number of bits of data per memory cell (and, therefore, the number of valid threshold voltage distributions) are increased, the data capacity of a memory device increases. However, the time needed for programming also increases. For example, the greater the number of valid threshold voltage distributions, the greater the number of verify operations needed between program pulses.